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<div class="title">EPHY (Ethernet PHY)</div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p>The PHY chip is outside of SoC. </p>
<p>It has 15 IEEE specified standard registers. The EPHY driver implements those standard registers. It provides an API for PHY management abstraction layer.</p>
<p>The functions and other declarations used in this driver are in cy_ephy.h. You can include cy_pdl.h (ModusToolbox only) to get access to all functions and declarations in the PDL.</p>
<dl class="section note"><dt>Note</dt><dd>Apart from IEEE standard registers, optionally it has some vendor specific extended registers. The EPHY driver does not implement extended registers. Any access to PHY registers can be done by using MAC driver APIs, i.e, <a class="el" href="group__group__ethif__functions.html#ga9516b412dd1dd99a5aceb26d89497f8a">Cy_ETHIF_PhyRegRead()</a> and <a class="el" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite()</a>.</dd></dl>
<h1><a class="anchor" id="group_ephy_configuration"></a>
Configuration Considerations</h1>
<p>Code snippet for Initializing DP83867IR PHY chip</p>
<div class="fragment"><div class="line"></div><div class="line"><span class="preprocessor">#define EMAC_MII                0</span></div><div class="line"><span class="preprocessor">#define EMAC_RMII               1</span></div><div class="line"><span class="preprocessor">#define EMAC_GMII               2</span></div><div class="line"><span class="preprocessor">#define EMAC_RGMII              3</span></div><div class="line"></div><div class="line"><span class="preprocessor">#define ETH_LINKSPEED_10        10</span></div><div class="line"><span class="preprocessor">#define ETH_LINKSPEED_100       100</span></div><div class="line"><span class="preprocessor">#define ETH_LINKSPEED_1000      1000</span></div><div class="line"></div><div class="line"><span class="comment">/********************************************************/</span></div><div class="line"><span class="comment">/* PHY Mode Selection      */</span></div><div class="line"><span class="preprocessor">#define EMAC_INTERFACE          EMAC_RGMII</span></div><div class="line"><span class="preprocessor">#define EMAC_LINKSPEED          ETH_LINKSPEED_1000</span></div><div class="line"><span class="comment">/*******************************************************/</span></div><div class="line"></div><div class="line"><span class="comment">/* PHY related constants   */</span></div><div class="line"><span class="preprocessor">#define PHY_ADDR                0</span></div><div class="line"><a class="code" href="structcy__stc__ephy__t.html">cy_stc_ephy_t</a> phyObj;</div><div class="line"></div><div class="line"><span class="comment">/*******************************************************/</span></div><div class="line"></div><div class="line"><span class="comment">/* MAC related constants   */</span></div><div class="line"><span class="preprocessor">#define ETH_REG_BASE            ETH1</span></div><div class="line"></div><div class="line"></div><div class="line"><span class="comment">/*******************************************************************************</span></div><div class="line"><span class="comment">* Function Name: snippet_Cy_EPHY_Read</span></div><div class="line"><span class="comment">****************************************************************************/</span></div><div class="line"><span class="keywordtype">void</span> snippet_Cy_EPHY_Read(uint32_t phyId, uint32_t regAddress, uint32_t *value)</div><div class="line">{</div><div class="line">    *value = <a class="code" href="group__group__ethif__functions.html#ga9516b412dd1dd99a5aceb26d89497f8a">Cy_ETHIF_PhyRegRead</a>(ETH_REG_BASE, regAddress, phyId);</div><div class="line">}</div><div class="line"></div><div class="line"></div><div class="line"><span class="comment">/*******************************************************************************</span></div><div class="line"><span class="comment">* Function Name: snippet_Cy_EPHY_Write</span></div><div class="line"><span class="comment">****************************************************************************/</span></div><div class="line"><span class="keywordtype">void</span> snippet_Cy_EPHY_Write(uint32_t phyId, uint32_t regAddress, uint32_t value)</div><div class="line">{</div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, regAddress, value, phyId);</div><div class="line">}</div><div class="line"></div><div class="line"><span class="comment">/*******************************************************************************</span></div><div class="line"><span class="comment">* Function Name: snippet_Cy_EPHY_DP83867IR_Init_ExtendedReg</span></div><div class="line"><span class="comment">****************************************************************************/</span></div><div class="line"><span class="keyword">static</span> <span class="keywordtype">void</span> snippet_Cy_EPHY_DP83867IR_Init_ExtendedReg(<span class="keywordtype">void</span>)</div><div class="line">{</div><div class="line"><span class="preprocessor">#if EMAC_LINKSPEED == ETH_LINKSPEED_100</span></div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x10, 0x5028, PHY_ADDR);                     <span class="comment">/* Disable auto neg for MDI/MDI-X **/</span></div><div class="line"><span class="preprocessor">#elif EMAC_LINKSPEED == ETH_LINKSPEED_1000</span></div><div class="line">    uint32_t    u32ReadData;</div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x0D, 0x001F, PHY_ADDR);                     <span class="comment">/* Begin write access to Extended register     */</span></div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x0E, 0x0170, PHY_ADDR);</div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x0D, 0x401F, PHY_ADDR);</div><div class="line">    u32ReadData = <a class="code" href="group__group__ethif__functions.html#ga9516b412dd1dd99a5aceb26d89497f8a">Cy_ETHIF_PhyRegRead</a>(ETH_REG_BASE, (uint8_t)0x0E, PHY_ADDR);</div><div class="line">    u32ReadData = u32ReadData &amp; 0x0000;                                             <span class="comment">/* changing IO impedance on the PHY    */</span></div><div class="line">    u32ReadData = u32ReadData | 0x010C;</div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x0E, u32ReadData, PHY_ADDR);                <span class="comment">/* Enable clock from PHY -&gt; Route it to MCU    */</span></div><div class="line">    u32ReadData = <a class="code" href="group__group__ethif__functions.html#ga9516b412dd1dd99a5aceb26d89497f8a">Cy_ETHIF_PhyRegRead</a>(ETH_REG_BASE, (uint8_t)0x0E, PHY_ADDR);</div><div class="line"><span class="preprocessor">#else</span></div><div class="line">    </div><div class="line"><span class="preprocessor">#endif </span><span class="comment">/* EMAC_LINKSPEED == ETH_LINKSPEED_100 */</span><span class="preprocessor"></span></div><div class="line"></div><div class="line">    <span class="comment">/* Disable RGMII by accessing extended register set || Please read data sheet section 8.4.2.1 for procedure in detail */</span></div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x0D, 0x001F, PHY_ADDR);                     <span class="comment">/* REGCR  */</span></div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x0E, 0x0032, PHY_ADDR);                     <span class="comment">/* ADDAR, 0x0032 RGMII config register  */</span></div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x0D, 0x401F, PHY_ADDR);                     <span class="comment">/* REGCR, will force next write/read access non incremental  */</span></div><div class="line"><span class="preprocessor">#if EMAC_INTERFACE != EMAC_RGMII</span></div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x0E, 0x0000, PHY_ADDR);                     <span class="comment">/* Disable RGMII  */</span></div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9516b412dd1dd99a5aceb26d89497f8a">Cy_ETHIF_PhyRegRead</a>(ETH_REG_BASE, (uint8_t)0x0E, PHY_ADDR);                     <span class="comment">/* Read the RGMII mode status  */</span></div><div class="line"><span class="preprocessor">#else</span></div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x0E, 0x00D3, PHY_ADDR);                     <span class="comment">/* Enable Tx and RX Clock delay in RGMII configuration register  */</span></div><div class="line"></div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x0D, 0x001F, PHY_ADDR);                     <span class="comment">/* REGCR  */</span></div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x0E, 0x0086, PHY_ADDR);                     <span class="comment">/* ADDAR, 0x0086 Delay config register  */</span></div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x0D, 0x401F, PHY_ADDR);                     <span class="comment">/* REGCR, will force next write/read access non incremental  */</span></div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x0E, 0x0066, PHY_ADDR);                     <span class="comment">/* Adjust Tx and Rn Clock delays in PHY  */</span></div><div class="line"></div><div class="line"><span class="preprocessor">#endif </span><span class="comment">/* EMAC_INTERFACE != EMAC_RGMII */</span><span class="preprocessor"></span></div><div class="line"></div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x1F, 0x4000, PHY_ADDR);         <span class="comment">/* CTRL   */</span></div><div class="line">    <a class="code" href="group__group__syslib__functions.html#gaad1c32546fdb0e3c6fa8b46fb95843b5">Cy_SysLib_Delay</a>(30);       <span class="comment">/* Some more delay to get PHY adapted to new interface   */</span></div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9516b412dd1dd99a5aceb26d89497f8a">Cy_ETHIF_PhyRegRead</a>(ETH_REG_BASE, (uint8_t)0x11, PHY_ADDR);</div><div class="line">}</div><div class="line"></div><div class="line"></div><div class="line"><span class="comment">/*******************************************************************************</span></div><div class="line"><span class="comment">* Function Name: snippet_Cy_EPHY_DP83867IR_Init</span></div><div class="line"><span class="comment">****************************************************************************/</span></div><div class="line"><span class="keywordtype">void</span> snippet_Cy_EPHY_DP83867IR_Init(<span class="keywordtype">void</span>)</div><div class="line">{</div><div class="line">    <a class="code" href="structcy__stc__ephy__config__t.html">cy_stc_ephy_config_t</a> phyConfig;</div><div class="line"></div><div class="line">    <span class="comment">/* 1. initialize phy: register  phy read and write callback functions */</span></div><div class="line">    <a class="code" href="group__group__ephy__functions.html#gab1637c80ec3ae7b2c4e6584dca117567">Cy_EPHY_Init</a>(&amp;phyObj, snippet_Cy_EPHY_Read, snippet_Cy_EPHY_Write);</div><div class="line"></div><div class="line">    <span class="comment">/* 2. PHY reset before configuring registers */</span></div><div class="line">    <a class="code" href="group__group__ephy__functions.html#ga4755f9c6f13d195c3cc598217904bdaf">Cy_EPHY_Reset</a>(&amp;phyObj); <span class="comment">/* reset IEEE standard registers */</span></div><div class="line">    <a class="code" href="group__group__ethif__functions.html#ga9f3890113dba441b3cd2e2d9a863c8a9">Cy_ETHIF_PhyRegWrite</a>(ETH_REG_BASE, 0x1F, 0x8000, PHY_ADDR); <span class="comment">/* Reset vendor specific (DP83867IR) Extended registers  */</span></div><div class="line">    <a class="code" href="group__group__syslib__functions.html#gaad1c32546fdb0e3c6fa8b46fb95843b5">Cy_SysLib_Delay</a>(30);    <span class="comment">/* Required some delay to get PHY back to Run state after Reset */</span></div><div class="line"></div><div class="line">    <span class="comment">/* 3. Fill PHY configure structure */</span></div><div class="line">    phyConfig.<a class="code" href="structcy__stc__ephy__config__t.html#a9fd7f090ee714f0b1261407cc8c079de">duplex</a> = <a class="code" href="group__group__ephy__enums.html#gga2bfa823cc961999293d4f74ab2bc1126a68e2cfea5bc06ec2ecebd32184f52998">CY_EPHY_DUPLEX_FULL</a>;</div><div class="line">    phyConfig.<a class="code" href="structcy__stc__ephy__config__t.html#acfd94590bef3641594ab42bd88c2d959">speed</a> = EMAC_LINKSPEED;</div><div class="line"></div><div class="line">    <span class="comment">/* 4. Configure IEEE standard PHY registers */</span></div><div class="line">    <a class="code" href="group__group__ephy__functions.html#ga4a2dcc3c1d82a0f1cbc2b699529a96f2">Cy_EPHY_Configure</a>(&amp;phyObj, &amp;phyConfig);</div><div class="line"></div><div class="line">    <span class="comment">/* 5. Configure vendor specific (DP83867IR) extended registers */</span></div><div class="line">    snippet_Cy_EPHY_DP83867IR_Init_ExtendedReg();</div><div class="line"></div><div class="line">}</div><div class="line"></div></div><!-- fragment --> <h1><a class="anchor" id="group_ephy_more_information"></a>
More Information</h1>
<p>Refer to the technical reference manual (TRM) and the device datasheet.</p>
<h1><a class="anchor" id="group_ephy_MISRA"></a>
MISRA-C Compliance</h1>
<p>The EPHY driver does not have any specific deviation</p>
<h1><a class="anchor" id="group_ephy_Changelog"></a>
Changelog</h1>
<table class="doxtable">
<tr>
<th>Version</th><th>Changes</th><th>Reason for Change </th></tr>
<tr>
<td>1.30 </td><td>Updated <a class="el" href="group__group__ephy__functions.html#gaadfc8591e97eb0c9e11199ba2b1da39a">Cy_EPHY_getLinkPartnerCapabilities</a> function.  </td><td>Bug fixes and code enhancement.  </td></tr>
<tr>
<td>1.20 </td><td>Changed naming conventions as per standard. </td><td>Code Enhancement.  </td></tr>
<tr>
<td>1.10 </td><td>Updated <a class="el" href="group__group__ephy__functions.html#ga4a2dcc3c1d82a0f1cbc2b699529a96f2">Cy_EPHY_Configure()</a> function and Added new macros for BMSR register. </td><td>Bug fixes and support enhancement for 1Gbps configuration.  </td></tr>
<tr>
<td>1.0 </td><td>Initial version </td><td></td></tr>
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